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LP3999 Low Noise 150mA Voltage Regulator for RF/Analog Applications
December 2003
LP3999 Low Noise 150mA Voltage Regulator for RF/Analog Applications
General Description
The LP3999 regulator is designed to meet the requirements of portable wireless battery-powered applications and will provide an accurate output voltage with low noise and low quiescent current. Ideally suited for powering RF/Analog devices this device will also be used to meet more general circuit requirements. For battery powered applications the low dropout and low ground current provided by the device allows the lifetime of the battery to be maximized.The inclusion of an Enable(disable) control can be used by the system to further extend the battery lifetime by reducing the power consumption to virtually zero. Should the application require a device with an active disable function please refer to device LP3995. The LP3999 also features internal protection against shortcircuit currents and over-temperature conditions. The LP3999 is designed to be stable with small 1.0 F ceramic capacitors. The small outline of the LP3999 micro SMD package with the required ceramic capacitors can realize a system application within minimal board area. Performance is specified for a -40C to +125C temperature range. The device is available in micro SMD package and LLP package. For other package options contact your local NSC sales office. The device is available in fixed output voltages in the ranges of 1.5V to 3.3V. For availability, please contact your local NSC sales office.
Key Specifications
n n n n n n n n 2.5V to 6.0V Input Range Accurate Output Voltage; 75mV / 2% 60 mV Typical Dropout with 150 mA Load. Vout > 2.5V Virtually Zero Quiescent Current when Disabled 10 Vrms output noise over 10Hz to 100kHz Stable with a 1 F Output Capacitor Guaranteed 150 mA Output Current Fast Turn-on Time; 140 s (Typ.)
Features
n n n n n n n 5 pin micro SMD Package 6 pin LLP Package Stable with Ceramic Capacitor Logic Controlled Enable Fast Turn-on Thermal-overload and short-circuit protection -40 to +125C junction temperature range for operation
Applications
n n n n n n GSM Portable Phones CDMA Cellular Handsets Wideband CDMA Cellular Handsets Bluetooth Devices Portable Information Appliances Handheld MP3 Devices
Typical Application Circuit
20052001
(c) 2003 National Semiconductor Corporation
DS200520
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LP3999
Block Diagram
20052002
Pin Description Package 5 pin micro SMD
Pin No. micro SMD A1 B2 C1 C3 A3 LLP 3 2 6 1 4 5 Pad VEN GND VOUT VIN CBYPASS N/C GND Enable Input; Disables the Regulator when 0.4V. Enables the regulator when 0.9V Common Ground Voltage output. Connect this output to the load circuit. Voltage Supply Input Bypass Capacitor connection. Connect a 0.01 F capacitor for noise reduction. No internal connection. There should not be any board connection to this pin. Ground connection. Connect to ground plane for best thermal conduction. Symbol Name and Function
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LP3999
Connection Diagrams
micro SMD, 5 Bump Package
20052003
See NS Package Number TLA05 LLP-6 Package (SOT23 footprint)
20052004
See NS Package Number LDE06A
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LP3999
Ordering Information
For micro SMD Package Output Voltage (V) 1.5 1.6 (Note 2) 1.7(Note 2) 1.8 1.875 1.9 (Note 2) 2.0(Note 2) 2.1 (Note 2) 2.2(Note 2) 2.4 2.5 2.6(Note 2) 2.8 3.0(Note 2) 3.3 Grade LP3999 Supplied as 250 Units, Tape and Reel LP3999ITL-1.5 LP3999ITL-1.6 LP3999ITL-1.7 LP3999ITL-1.8 LP3999ITL-1.875 LP3999ITL-1.9 LP3999ITL-2.0 LP3999ITL-2.1 LP3999ITL-2.2 LP3999ITL-2.4 LP3999ITL-2.5 LP3999ITL-2.6 LP3999ITL-2.8 LP3999ITL-3.0 LP3999ITL-3.3 For micro SMD Package UNLEADED Output Voltage (V) 1.5 (Note 2) 1.6 (Note 2) 1.7 (Note 2) 1.8 (Note 2) 1.875 (Note 2) 1.9 (Note 2) 2.0(Note 2) 2.1 (Note 2) 2.2(Note 2) 2.4 (Note 2) 2.5 (Note 2) 2.6(Note 2) 2.8 (Note 2) 3.0(Note 2) 3.3(Note 2) Grade LP3999 Supplied as 250 Units, Tape and Reel LP3999ITL-1.5 NOPB LP3999ITL-1.6 NOPB LP3999ITL-1.7 NOPB LP3999ITL-1.8 NOPB LP3999ITL-1.875 NOPB LP3999ITL-1.9 NOPB LP3999ITL-2.0 NOPB LP3999ITL-2.1 NOPB LP3999ITL-2.2 NOPB LP3999ITL-2.4 NOPB LP3999ITL-2.5 NOPB LP3999ITL-2.6 NOPB LP3999ITL-2.8 NOPB LP3999ITL-3.0 NOPB LP3999ITL-3.3 NOPB LP3999 Supplied as 3000 Units, Tape and Reel LP3999ITLX-1.5 NOPB LP3999ITLX-1.6 NOPB LP3999ITLX-1.7 NOPB LP3999ITLX-1.8 NOPB LP3999ITLX-1.875 NOPB LP3999ITLX-1.9 NOPB LP3999ITLX-2.0 NOPB LP3999ITLX-2.1 NOPB LP3999ITLX-2.2 NOPB LP3999ITLX-2.4 NOPB LP3999ITLX-2.5 NOPB LP3999ITLX-2.6 NOPB LP3999ITLX-2.8 NOPB LP3999ITLX-3.0 NOPB LP3999ITLX-3.3 NOPB Package Marking LP3999 Supplied as 3000 Units, Tape and Reel LP3999ITLX-1.5 LP3999ITLX-1.6 LP3999ITLX-1.7 LP3999ITLX-1.8 LP3999ITLX-1.875 LP3999ITLX-1.9 LP3999ITLX-2.0 LP3999ITLX-2.1 LP3999ITLX-2.2 LP3999ITLX-2.4 LP3999ITLX-2.5 LP3999ITLX-2.6 LP3999ITLX-2.8 LP3999ITLX-3.0 LP3999ITLX-3.3 Package Marking
STD STD STD STD STD STD STD STD STD STD STD STD STD STD STD
STD STD STD STD STD STD STD STD STD STD STD STD STD STD STD
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LP3999
Ordering Information
Output Voltage (V) 1.5 (Note 2) 1.6(Note 2) 1.8 (Note 2) 1.875(Note 2) 1.9 (Note 2) 2..0 (Note 2) 2.1 (Note 2) 2.2 (Note 2) 2.4 (Note 2) 2.5 (Note 2) 2.6 (Note 2) 2.8 (Note 2) 3.0 (Note 2) 3.3 (Note 2) Grade
(Continued) For LLP-6 Package LP3999 Supplied as 1000 Units, Tape and Reel LP3999ILD-1.5 LP3999ILD-1.6 LP3999ILD-1.8 LP3999ILD-1.875 LP3999ILD-1.9 LP3999ILD-2.0 LP3999ILD-2.1 LP3999ILD-2.2 LP3999ILD-2.4 LP3999ILD-2.5 LP3999ILD-2.6 LP3999ILD-2.8 LP3999ILD-3.0 LP3999ILD-3.3 LP3999 Supplied as 4500 Units, Tape and Reel LP3999ILDX-1.5 LP3999ILDX-1.6 LP3999ILDX-1.8 LP3999ILDX-1.875 LP3999ILDX-1.9 LP3999ILDX-2.0 LP3999ILDX-2.1 LP3999ILDX-2.2 LP3999ILDX-2.4 LP3999ILDX-2.5 LP3999ILDX-2.6 LP3999ILDX-2.8 LP3999ILDX-3.0 LP3999ILDX-3.3 L038B L039B L040B L037B L036B L035B Package Marking L032B L033B L034B
STD STD STD STD STD STD STD STD STD STD STD STD STD STD
Note 1: Available in sample quantities only Note 2: For availability contact your local sales office
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LP3999
Absolute Maximum Ratings
(Notes 3, 4) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Input Voltage (VIN) Output Voltage Enable Input Voltage Junction Temperature Lead/Pad Temperature (Note 5) LLP microSMD Storage Temperature Continuous Power Dissipation (Note 6) 235C 260C -65 to +150C Internally limited -0.3 to 6.5V -0.3 to (VIN + 0.3V) to 6.5V (max) -0.3 to 6.5V 150C
ESD (Note 9) Human Body Model Machine Model 2 kV 200V
Operating Ratings (Note 3)
Input Voltage (VIN) Enable Input Voltage Junction Temperature Ambient Temperature Range (Note 7) 2.5 to 6.0V 0 to 6.0V -40 to +125C -40 to 85C
Thermal Properties(Note 8)
Junction to Ambient Thermal Resistance JA (LLP pkg.) JA (micro SMD pkg.) 88C/W 255C/W
Electrical Characteristics
Unless otherwise noted, VEN = 1.5, VIN = VOUT(NOM) + 1.0V, CIN = 1 F, IOUT = 1 mA, COUT = 1 F, cBP = 0.01 F. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the full temperature range for operation, -40 to +125C. (Note 13) Symbol VIN VOUT Parameter Input Voltage Output Voltage Tolerance Line Regulation Error micro SMD Load Regulation Error LLP Load Regulation Error PSRR Power Supply Rejection Ratio (Note 11) Output Voltage Tolerance microSMD Line Regulation Error LLP Line Regulation Error micro SMD Load Regulation Error LLP Load Regulation Error PSRR Power Supply Rejection Ratio (Note 11) IOUT = 1 mA VIN = (VOUT(NOM)+1.0V) to 6.0V, IOUT = 1 mA IOUT = 1 mA to 150 mA IOUT = 1 mA to 150 mA f = 1 kHz, IOUT = 1 mA f = 10 kHz, IOUT = 1 mA IOUT = 1 mA VIN = (VOUT(NOM)+1.0V) to 6.0V, IOUT = 1 mA VIN = (VOUT(NOM)+1.0V) to 6.0V, IOUT = 1 mA IOUT = 1 mA to 150 mA IOUT = 1 mA to 150 mA f = 1 kHz, IOUT = 1 mA f = 10 kHz, IOUT = 1 mA 10 80 60 60 10 70 58 58 -50 -75 -2.5 -3.5 50 75 2.5 3.5 75 125 Conditions Typical Limit Min 2.5 -50 -75 -3.5 Max 6.0 50 75 3.5 75 125 Units V
DEVICE OUTPUT: 1.5 VOUT < 1.8V mV mV/V V/mA V/mA dB
DEVICE OUTPUT: 1.8 VOUT < 2.5V VOUT mV mV/V mV/V V/mA V/mA dB
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LP3999
Electrical Characteristics
(Continued) Unless otherwise noted, VEN = 1.5, VIN = VOUT(NOM) + 1.0V, CIN = 1 F, IOUT = 1 mA, COUT = 1 F, cBP = 0.01 F. Typical values and limits appearing in normal type apply for TJ = 25C. Limits appearing in boldface type apply over the full temperature range for operation, -40 to +125C. (Note 13) Symbol Parameter Conditions Typical Limit Min -2 -3 Line Regulation Error micro SMD Load Regulation Error LLP Load Regulation Error Dropout Voltage VIN = (VOUT(NOM)+1.0V) to 6.0V, IOUT = 1 mA IOUT = 1 mA to 150 mA IOUT = 1 mA to 150 mA IOUT = 1 mA IOUT = 150 mA f = 1 kHz, IOUT = 1 mA f = 10 kHz, IOUT = 1 mA (Notes 10, 11) VEN = 1.5V, IOUT = 0 mA VEN = 1.5V, IOUT = 150 mA VEN = 0.4V 85 140 0.003 450 10 30 160 20 Vrms 0.0004 0.003 0.4 60 60 50 0 150 200 1.5 mA A 2 100 -0.1 Max 2 3 0.1 0.002 Units
DEVICE OUTPUT: 2.5 VOUT 3.3V VOUT Output Voltage Tolerance IOUT = 1 mA % of VOUT(NOM) %/V %/mA %/mA mV dB
PSRR
Power Supply Rejection Ratio (Note 11) Load Current Quiescent Current
FULL VOUT RANGE ILOAD IQ A
ISC EN
Short Circuit Current Limit Output Noise Voltage ((Note 11)) BW = 10 Hz to 100 kHz, VIN = 4.2V, No Load BW = 10 Hz to 100 kHz, VIN = 4.2V, 1mA Load
TSHUTDOWN
Thermal Shutdown
Temperature Hysteresis
C
ENABLE CONTROL CHARACTERISTICS IEN VIL VIH TON Maximum Input Current at VEN Input Low Input Threshold High Input Threshold Turn On Time (Note 11) To 95% Level (Note 12) 140 0.9 VEN = 0.0V and VIN = 6.0V 0.001 0.4 A V V s
TIMING CHARACTERISTICS
Note 3: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 4: All voltages are with respect to the potential at the GND pin. Note 5: For further information on these packages please refer to the following application notes; AN-1112 Micro SMD Package Wafer Level Chip Scale Package, AN-1187. Leadless Leadframe Package. Note 6: Internal Thermal shutdown circuitry protects the device from permanent damage. Note 7: In applications where high power dissipation and/or poor thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op)), the maximum power dissipation (PD(max)), and the junction to ambient thermal resistance in the application (JA). This relationship is given by :-
TA(max) = TJ(max-op) - (PD(max) x JA)
Note 8: Junction to ambient thermal resistance is highly dependant on the application and board layout. In applications where high thermal dissipation is possible, special care must be paid to thermal issues in the board design. Note 9: The human body is 100 pF discharge through 1.5 k resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. Note 10: The device maintains the regulated output voltage without load. Note 11: This electrical specification is guaranteed by design. Note 12: Time from VEN = 0.9V to VOUT = 95% (VOUT(NOM))
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LP3999
Electrical Characteristics
(Continued)
Note 13: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production at TJ = 25C or correlated using Statistical Quality Control methods. Operation over the temperature specification is guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 14: VOUT(NOM) is the stated output voltage option for the device.
Recommended Output Capacitor
Symbol COUT Parameter Output Capacitor Conditions Capacitance (Note 15) ESR Typical 1.0 Limit Min 0.75 5 500 Max Units F m
Note 15: The capacitor tolerance should be 30% or better over temperature. Recommended capacitor type is X7R however dependant on application X5R,Y5V and Z5U can also be used.
Input Test Signals
20052006
FIGURE 1. Line Transient Response Input Test Signal
20052007
FIGURE 2. PSRR Input Test Signal
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LP3999
Typical Performance Characteristics
VIN = VOUT + 1.0V, TA = 25C, Enable pin is tied to VIN. Output Voltage Change vs Temperature
Unless otherwise specified, CIN = COUT = 1.0 F Ceramic, Ground Current vs Load Current (1.8V VOUT)
20052010
20052011
Ground Current vs VIN @ 25C
Ground Current vs VIN @125C
20052014
20052015
Ground Current vs VIN @ -40C
Short Circuit Current
20052016 20052013
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LP3999
Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1.0 F Ceramic, VIN
= VOUT + 1.0V, TA = 25C, Enable pin is tied to VIN. (Continued) Line Transient Response (1.8V VOUT) Line Transient Response (1.5V VOUT)
20052018
20052017
Ripple Rejection (1.8V VOUT)
Ripple Rejection (1.5V VOUT)
20052019
20052020
Enable Start-Up Time (VOUT = 1.8V)
Enable Start-Up Time (VOUT = 1.8V)
20052030
20052031
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LP3999
Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1.0 F Ceramic, VIN
= VOUT + 1.0V, TA = 25C, Enable pin is tied to VIN. (Continued) Enable Start-Up Time (VOUT = 1.5V) Enable Start-Up Time (VOUT = 1.5V)
20052032
20052033
Load Transient Response (VOUT = 1.8V)
Load Transient Response (VOUT = 1.5V)
20052022
20052021
Output Noise Density VIN = 4.2V VOUT = 2.5V)
20052034
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LP3999
Application Hints
POWER DISSIPATION AND DEVICE OPERATION The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die and ambient air. As stated in (Note 7) in the electrical specification section, the allowable power dissipation for the device in a given package can be calculated using the equation:
OUTPUT CAPACITOR The LP3999 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types Z5U, Y5V or X7R) in the 1.0 [to 10 F] range, and with ESR between 5 m to 500 m, is suitable in the LP3999 application circuit. For this device the output capacitor should be connected between the VOUT pin and ground. It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as attractive for reasons of size and cost (see the section Capacitor Characteristics). The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5 m to 500 m for stability. NO-LOAD STABILITY The LP3999 will remain stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications. CAPACITOR CHARACTERISTICS The LP3999 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 1 F to 4.7 F, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1 F ceramic capacitor is in the range of 20 m to 40 m, which easily meets the ESR requirement for stability for the LP3999. The temperature performance of ceramic capacitors varies by type. Most large value ceramic capacitors ( 2.2 F) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25C to 85C. A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable and holds the capacitance within 15% over the temperature range. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1 F to 4.7 F range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25C down to -40C, so some guard band must be allowed. NOISE BYPASS CAPACITOR A bypass capacitor should be connected between the CBYPASS pin and ground to significantly reduce the noise at the regulator output. This device pin connects directly to a high impedance node within the bandgap reference circuitry. Any significant loading on this node will cause a change on the regulated output voltage. For this reason, DC leakage current through this pin must be kept as low as possible for best output voltage accuracy. The use of a 0.01F bypass capacitor is strongly recommended to prevent overshoot on the output during start-up.
With a JA = 255C/W, the device in the micro SMD package returns a value of 392 mW with a maximum junction temperature of 125C. The actual power dissipation across the device can be represented by the following equation: PD = (VIN - VOUT) x IOUT. This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. These two equations should be used to determine the optimum operating conditions for the device in the application. EXTERNAL CAPACITORS In common with most regulators, the LP3999 requires external capacitors to ensure stable operation. The LP3999 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. INPUT CAPACITOR An input capacitor is required for stability. It is recommended that a 1.0 F capacitor be connected between the LP3999 input pin and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain 1.0 F over the entire operating temperature range.
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LP3999
Application Hints
(Continued)
The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High quality ceramic capacitors with NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low leakage current. Unlike many other LDO's, the addition of a noise reduction capacitor does not effect the transient response of the device. ENABLE OPERATION The LP3999 may be switched ON or OFF by a logic input at the ENABLE pin, VEN. A high voltage at this pin will turn the device on. When the enable pin is low, the regulator output is off and the device typically consumes 3 nA. If the application does not require the shutdown feature, the VEN pin should be tied to VIN to keep the regulator output permanently on. To ensure proper operation, the signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. FAST TURN ON Fast turn-on is guaranteed by control circuitry within the reference block allowing a very fast ramp of the output voltage to reach the target voltage. There is no active turn-off on this device. Refer to LP3995 for a similar device with active turn-off.
micro SMD MOUNTING The micro SMD package requires specific mounting techniques which are detailed in National Semiconductor Application Note AN-1112. Referring to the section Surface Mount Technology (SMT) Assembly Considerations, it should be noted that the pad style which must be used with the 5 pin package is NSMD (non-solder mask defined) type. For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the micro SMD device. micro SMD LIGHT SENSITIVITY Exposing the micro SMD device to direct sunlight will cause incorrect operation of the device. Light sources such as halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with wavelengths in the red and infra-red part of the spectrum have the most detrimental effect thus the fluorescent lighting used inside most buildings has very little effect on performance. Tests carried out on a micro SMD test board showed a negligible effect on the regulated output voltage when brought within 1 cm of a fluorescent lamp. A deviation of less than 0.1% from nominal output voltage was observed.
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LP3999
Physical Dimensions
inches (millimeters) unless otherwise noted
micro SMD, 5 Bump, Package (TLA05) NS Package Number TLA05ADA The dimensions for X1, X2 and X3 are given as: X1 = 1.006 +/- 0.03mm X2 = 1.438 +/- 0.03mm X3 = 0.600 +/- 0.075mm
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LP3999 Low Noise 150mA Voltage Regulator for RF/Analog Applications
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
LLP, 6 Lead, Package (SOT23 Land) NS Package Number LDE06A
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ``Banned Substances'' as defined in CSP-9-111S2.
National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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